1. Field of the Invention
The present invention relates generally to the field of electronic data storage devices. More particularly, the present invention relates to non-volatile semiconductor memory devices having a compact threshold voltage distribution and a method for compacting the threshold voltage distribution for non-volatile semiconductor memory designs.
2. Description of the Related Art
Electronic data storage designs, referred to as memory, are used to store computer programs executed by an electronic processor and/or store logical data operated on by the processor to achieve the functionality of an electronic device. Semiconductor memory designs that do not require ambient power to store electronic data, commonly referred to as xe2x80x9cnon-volatilexe2x80x9d semiconductor memory devices, have been developed. Flash memory is a specific form of non-volatile memory by which bits of logical data are stored in units of memory termed memory cells. A grouping of memory cells is termed a word, a grouping of words termed a page, and a grouping of pages termed a sector. Data is accessed for reading and programming by word or page, while an entire sector must be accessed for erasing. In general, the flash memory is arranged into columns and rows of memory cells, each column representing a bitline of a data.
A typical memory cell in a flash memory device includes a transistor characterized by a programmable threshold voltage Vt. The transistor""s threshold voltage can be set, or programmed, to a desired value along an analog scale between maximum and minimum threshold voltage limits that are determined based on the design parameters for the transistor. In one example, a flash memory cell has a discrete Metal-Oxide-Semiconductor (xe2x80x9cMOSxe2x80x9d) field effect transistor having a source, a drain, a floating gate, a control gate and a p-well substrate material. In conventional flash memory designs, known as NOR memory, the memory cells are arranged in an array of rows and columns, with the control gates of the transistors comprising a row being electrically coupled to a respective word-line and the drains comprising a column being electrically coupled to a respective bit-line. The sources of each memory cell are electrically coupled to each other.
Voltages can be applied to the transistor for setting the Vt to represent logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0,xe2x80x9d for reading the data stored in the memory cell, for verifying that the cell is programmed, for verifying that the cell is erased, and for verifying that the cell is not overerased. When a voltage sufficiently exceeding the Vt is applied to the control gate, the transistor turns on and can be caused to conduct substantial current. Conversely, when a voltage applied to the gate does not sufficiently exceed the Vt, the transistor will remain in an off state and will not conduct substantial current. In typical flash memory designs, the on state represents a logical xe2x80x9c1xe2x80x9d while the off state represents a logical xe2x80x9c0.xe2x80x9d For example, during a read cycle of a programmed memory cell, the voltage applied to the gate is not greater than Vt and the memory cell will not conduct current. In comparison, an erased memory cell will conduct current during a read cycle because the gate voltage is greater than Vt. Thus a programmed memory cell represents logical xe2x80x9c0,xe2x80x9d while and erased memory cell represents logical xe2x80x9c1.xe2x80x9d
In one example of a floating gate cell, the transistor is programmed by biasing the transistor in a manner to cause injection of electrons into the floating gate, and erased by biasing the transistor in a manner to cause electrons to evacuate the floating gate. In an example of a non-floating gate cell, a transistor with a thin insulating film between the substrate and control gate is programmed by biasing the transistor in a manner to cause injection of electrons to the thin insulating film, and erased by causing electrons to evacuate the thin insulating film. In general, electrons injected into the floating gate or the thin insulating film raises the Vt, while evacuation of electrons decreases the Vt.
By way of example, programming of the memory cell occurs by biasing the memory cell such that 9V is applied to the control gate, 5V is applied to the drain and the source is grounded (0V). This configuration causes electrons to be injected from the drain depletion region into the floating gate. After the memory cell is programmed the injected electrons are trapped, creating a negative charge that increases the Vt of the memory cell. By way of example, a programmed memory cell has a Vt greater than approximately 5V.
In one arrangement for reading data, the memory cell is biased by applying 5V to the word-line to which the control gate of the cell is connected, applying 1V to the bit-line to which the drain is connected, grounding the source, and sensing data on the bit-line. When data is read from a programmed memory cell, wherein Vt is set relatively high (5V), the bit-line to which it is electrically coupled will not conduct substantial current. In comparison, when data is read from an erased memory cell, wherein Vt is set relatively low, the control gate voltage creates a channel in which relatively high current will conduct on the bit line to which the erased memory cell is electrically coupled.
Erasure of data is caused by a process in which the transistor is biased in a manner to cause electrons to evacuate the floating gate or the thin insulating film, or by injection of holes into these regions. An erase voltage is applied at sufficient value and for a sufficient duration to lower the transistor""s threshold voltage below that of a predetermined voltage, often referred to as the erase-verify voltage (xe2x80x9cVcvxe2x80x9d). The erase-verify voltage is sufficiently less than the voltage applied during the read cycles Vt so that an erased transistor will conduct current during a read cycle. In one arrangement for erasing, a relatively high voltage, typically 12V, is applied to the source while the gate is grounded and the drain is floating. This arrangement causes electrons to undergo Fowler-Nordheim tunneling from the floating gate towards the source. In another arrangement, the memory cell is biased with a negative voltage substantially on the order of xe2x88x9210V applied to the control gate while +10V is applied to the source and the drain is floating. In a further arrangement, 5V is applied to a P-well and xe2x88x9210V is applied to the control gate while the source/drain are floating. Although present flash memory designs can be erased at the sector level and can be programmed at the word level, it will be appreciated that the granularity by which a flash memory device can be programmed or erased may vary and that granularities down to the bit level are contemplated.
During erasure of a flash memory, the threshold voltage of each memory cell is verified to have a value less than the erase verify voltage. Because of variations in the physical and electrical characteristics of the memory cells, the rate that a memory cell erases can vary. Design variables such as channel length and width affect how fast a transistor can be erased. Because each memory cell is subjected to substantially the same erase voltage pulse, some memory cells erase faster than others. Fast-erase memory cells can overerase, having a lower threshold voltage than a slow-erase memory cell. The erased memory cells collectively form a threshold voltage distribution with the fast-erase memory cells having a relatively low threshold voltage, slow-erase memory cells having a threshold voltage closer to the erase verify voltage and typical memory cells having a median erased threshold voltage. A typical distribution will be centered about the median threshold voltage.
An overerased memory cell exhibits behavior similar to a depletion mode type transistor that cannot be turned off by normal operating voltages applied to the control gate, and may introduce leakage currents during subsequent program and read operations. Furthermore, a transistor with an undesirably low threshold voltage will have a larger sub-threshold current, also adding to the leakage current. Excessive leakage currents have adverse effects on the operation of the flash memory. For example, the leakage currents of multiple cells in a column have a summing effect of leakage current on the bit-line, and may result in an incorrect data reading. During programming, high column leakage due to cells having a high drain induced barrier lowering and/or a low erased threshold voltage, will result in large programming currents. Advanced Flash memory designs, utilizing shorter channel lengths, have been somewhat limited by drain induced barrier lowering and leakage currents of fast erase memory cells. As a result, minimizing the amount of low threshold voltage erased memory cells is desirable.
Accordingly, there is a need for providing a compact erased threshold voltage distribution for non-volatile semiconductor memory designs.
By way of introduction only, the present invention provides a method and apparatus for compacting a threshold voltage distribution of erased memory cells in a flash memory array. A flash memory array having a compact threshold voltage distribution will have reduced sub-threshold-voltage currents.
An illustrated example for a device of the present invention comprises a flash memory device having a plurality of memory cells configured to electronically store logical data and a circuitry electrically coupled to the memory cells configured to selectively soft program erased memory cells. The flash memory device is also configured to erase the memory cells subsequent to soft-programming. The memory cells are generally characterized as having a variable threshold voltage which can be set to one of at least two states: 1) an erased state, and 2) a programmed state. Erased memory cells have a threshold voltage set below a voltage limit, commonly referred to as an erase-verify voltage.
In general, erasing a memory cell comprises applying a voltage to the memory cell to lower its threshold voltage, while programming is designed to raise the threshold voltage. Because of variations in construction, memory cells will erase at various rates, with the fast-erase memory cells set to a lower threshold voltage than slow-erase memory cells. In an array of erased flash memory cells, many of the memory cells will have a threshold voltage substantially that of a median erase threshold voltage, fast erase memory cells will have a substantially lower threshold voltage, while slow erase memory cells will have a greater threshold voltage. A soft-programming circuit electrically coupled to the memory array is configured to apply soft-programming to memory cells having a threshold voltage less than a selected reference voltage. The selected reference voltage is chosen so that fast erase memory cells will be soft-programmed. Soft-programming, or partial programming, sets the threshold voltage of the fast erase cells to a value greater than the selected reference voltage. Subsequent to selectively soft-programming of the fast erase memory cells, the plurality of memory cells can then be erased in a manner known in the art. The device may then undergo another soft-program step using a second reference voltage level, if required. The resulting array has a compact erased threshold voltage distribution with the median erased threshold voltage greater than a non-compacted flash memory array. Accordingly, the device of the present invention provides an erased flash memory array with a higher median threshold voltage and fast erase bits having a higher threshold voltage than in a flash memory having conventionally erased memory cells.
An illustrated example for a method of the present invention provides for compacting a threshold voltage distribution for a flash memory design having a plurality of erased memory cells. The method includes selectively soft-programming a plurality of fast erased bits having a threshold voltage less than a selected reference voltage and subsequent to selectively soft-programming the memory cells, erasing the plurality of memory cells. The fast-erase bits may be soft-programmed again, using a second reference voltage level as required, to ensure a compacted erased threshold voltage distribution.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.